VERIFICATION'S

PHYSICAL VERIFICATION:
IN PHYSICAL VERIFICATION IT CHECKS:

1. LVS(LAYOUT VERSUS SCHEMATIC)
2. DRC(DESIGN RULE CONSTRAINTS CHECK)
3. ERC(ELECTRICAL RULE CHECK)

LAYOUT VERSUS SCHEMATIC(LVS):

INPUTS ARE (.LVS.V) AND (.GDSII) FILES AND RULE DECK FILES. 

COMPARISION TWO ELECTRICAL CIRCUITS EQUIVALENT WITH RESPECT TO THEIR "CONNECTIVITY" AND "TOTAL TRANSISTOR COUNT".

COMPARISION BETWEEN (.GDSII) FILE AND EXTRCTED NETLIST (.LVS.V) FILE.

FINALLY BOTH ARE CONVERTED INTO A SPICE LEVEL .

LVS CHECKS ARE:

EXTRACT ERRORS :

• SHORTS
• OPENS
• FLOATING NETS.

COMPARE ERRORS:

• PIN ERRORS
• PARAMETRIC ERRORS
• DEVICE MISMATCH
• NET MISMATCH
• MALFORMED DEVICES
• PORTS MISMATCH

DESIGN RULE CONSTARINTS CHECK(DRC):

INPUT IS .GDSII FILE AND RULE DECK FILE.

CHECKS:

• ACTIVE TO ACTIVE SPACINGS.
• WELL TO WELL SPACINGS.
• MINIMUM CHANNEL LENGTH OF THE TRANSISTOR.
• MINIMMUM METAL WIDTH.
• METAL TO METAL SPACINGS.
• ESD(ELECTRO STATIC DISCHARGE).
• I/O RULES.
• METAL FILL DENSITY.

ELECTRICAL RULE CHECK(ERC):

INPUT IS  (.GDSII) FILE .

INVOLVES CHECKING A DESIGN FOR ALL ELECTRICAL CONNECTIONS.

CHECKS ARE:

• WELL AND SUBSTRATE AREAS FOR PROPER CONTACTS AND SPCINGS THERE BY ENSURING CORRECT POWER CONTACTS AND GROUND CONNECTIONS.
• TO LOCATE FLOATING DEVICES AND FLOATING WELLS.
• TO LOCATE DEVICE WICH ARE SHORTED.
• TO LOCATE DEVICES WITH MISSING CONNECTIONS.
• GATE CONNECTRD DIRECTLY TO SUPPLIES.
• FLOATING INPUTS.

FORMAL VERIFICATIONS:

IN FORMAL VERIFICATION CHECKS ARE LEC(LOGICAL EQUIVALENCE CHECK).

CHECKING BETWEEN FINALLY EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

INPUTS ARE EXTRCCTED NETLIST(.V) AND SYNTHESIZED NETLIST(.V).

HERE CHECKING FOR FUNCTIONALITY CORRECTNESS.

DIFFERENT FILES IN PHYSICAL DESIGN
FILES:

1. LOGICAL LIBRARIES---------------------------> .lib, .db
2. PHYSICAL LIBRARIES ------------------------->.lef, .milkyway (OR) .volcano (OR), .plib(OR).enc
3. TECHNOLOGY FILE ----------------------------> .tf
4. TLU+ -------------------------------------------------->.tlup
5. INTER CONNECT TECHNOLOGY FILE ------> .itf
6. MAPPING FILE ------------------------------------> .map
7. NETLIST ---------------------------------------------> .v,(OR) .ddc ,(OR) .db, (OR) .EDIF
8. SDC-----------------------------------------------------> .sdc
9. PHYSICAL ONLY PAD CELLS PLACEMENT FILE ---------------------> .tdf
10. SCAN CHAIN FILE -------------------------------> .scandef
11. TOGGLE RATE FILE------------------------------>.saif, (OR) .vcd
12. ECO FILE ----------------------------------------->.eco
13. GDS FILE------------------------------------------>.gds
14. LOG FILE------------------------------------------>.log
15. REPORT FILE-------------------------------------->.rep
16. DESIGN EXCHANGE FORMAT------------------>.def
17. STANDARD DELAY FORMAT------------------->.sdf
18. STANDARD PARASITIC EXCHANGE FORMAT---------> .spef