LOGIC LIBRARIES

Logical libraries :Format is .lib(liberty)

1. Timing information of Standard cells,Soft macros,Hard macros.
2. Functionality  information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold,Recovery,Removal time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.
8. Functionality  is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out put voltage.

And PVT contains ------------>On Chip Variations(BC,WC)
                                ------------>Cell leakage Power
                                   ---------->Internal Power
                                   ---------->Rise Transition
                                  ----------->Fall transition
                                   ---------->>Setup rise
                                  ----------->Setup fall
                                  ----------->Hold rise
                                 ------------>Hold fall
                                 ------------>Minimum pulse width high
                                ------------->Minimum pulse width low
                                ------------->Recovery rise
                               -------------->Removal fall
                              --------------->Cell rise
                                -------------->Cell fall
                                -------------->Pin Capacitance

Cell level information 

1. Cell name
2. Area(represent with Nand Equ Area)
3. Power (Funtion of input transition, Total output net Cap )
4. Funtionality
5. Delay
6. Max Cap
7. Max Trans
8. Foot Print

And it also Contains K-Factor

And it also contain WIRE LOAD MODELS

And it contains A view(sub directory) i.e. LM(Logical Model view)view.
It contains logical libraries.

TECHNOLOGY FILE

Technology file: format is .tf:

1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of  layer and via
3. In Physical characteristics Min width,Min Spacing,Min Hight are present.
4. In Electrical characteristics Max Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

Layer Info :

1. Mask Name
2. Visible
3. Selectable
4. Line Style(Solid)
5. Patteren 
6. Pitch
7. Cut Layer 

PHYSICAL LIBRARIES

Physical libraries: format is .lef(Layout Exchange Format):

1. physical information of std cells,macros,pads.
2. Pin information.
3. Define unit tile(sites) placement.
4. Minimum Width of Resolution.
5. Hight of the placement Rows .
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antena Rules.
9. Routing Blockages,Macro Blockage

Macro/Stad Cells :-------------->Cell neame

                                -------------->Size(Dimensions,Area)

                                 ------------->Pin

                                 ------------->Port

                                  ------------->Layer

                                  ------------->Direction

                                  

Pins information :  --------------->Direction(Input,Output,INOUT)

                                 --------------->Use(Signal,Power,Ground)

                                 --------------->Antena Gate Area

                                 --------------->layer

  

LEFs are 3 Types :  .Macro lef (Macro Info)

                                  .StdCell lef(Standard Cell Info )

                                  .Tech lef(Layer,Via Info)

In physical info height,area,width are present.
and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

FINAL VERIFICATION GDS FILE EXPORT

FINAL VERIFICATION:

1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL DELAYS. TOOL:STAR RC XT LICENCE
2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL. 
3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.

AFTER VERIFICATION:

1. AFTER THIS WE RELEASE THE GDS FILE 
2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.

AFTER GDS 

AFTER THIS WE ARE FINALLY BASE TAPE OUT(BTO).

AFTER BASE TAPE OUT WE WILL DO METAL TAPE OUT(MTO).