Verification checks

DRC : Design rule check.

Design rule are strict guideline for drawing layout

• Minimum width
• Minimum spacing
• Minimum extension
• Minimum area (of metal requires to keep during Fab)
• Minimum jog
• Minimum notch

inputs to DRC:

• GDS data (layout net list)
• Rule deck file
• Rule check
• Layer map information: for designing a mask each layer will be given number on that number mask will be design.

LVS: layout vs schematic

compared the Drew shape of layout with schematic.

• Short : Two or more wire should not be connected together.
• Device Mismatch : Components of an incorrect type have been used (Low vt mos device are place instead of high vt cells).
• Missing device: An expected device has been left out of the layout.
• Property Mismatch: A component is the wrong size compare to schematic (bard peak feature).

Inputs to LVS:

• GDS (layout net list)
• Schematic netlist
• Rule deck file.

What is the soft connection / error?

This error come comes under ERC check.

Two or more nets are connected with high resistive layer ( well ) their this error will flog.

if two PMOS say p1 and p2 are placed in a single NWELL, if the taps of p1 and p2 are floating/ not connected to each other. but through NWELL both p1 and p2 are connected / shorted. this connection is soft connection error.

Avoid : you have to connect taps to vdd / vss through metal only.

What is the ERC?

ERC is stand for Electrical rule check : where electron get interacted their this error will flog.

ERC Rules check for things such as:

• Floating gates.
• Wrong transistor connections (Source and Drain connected together for instance).
• Floating interconnect, Metal, Poly
• Shorted Drain & Source of a MOS
• No substrate- or well contact ('figure having no stamped connection')
• Different contacts of substrate / well are connected to different nets
• Floating gate error – If any gate is unconnected, this could lead to leakage issues.
• VDD/VSS errors – The well geometries need to be connected to power/Ground and if the PG connection is not complete or if the pins are not defined, the whole layout can report errors like “NWELL not connected to VDD.

What is the EM check?

 EM is stands for Electromigration.

It's Usually occur in interconnection of the metal or metal bending, due to high current is flowing through the metal, as a long time, metal atom get migrated from original place or position, due to high electric filed, lock of ions are forming in this metal, cause that metal will short or open. This is reliability issue where we have to check for life of ic…

This density depends on the magnitude of forces that tend to hold the ions in place.

current density, temperature and mechanical stress. Elecromigration creates void (open circuit) and hillock (short circuit).

EM dependency on physical effects:

Temperature: once a void begins to develop in a metal wire, the wire itself becomes narrower at that point. Due to the reduction of width current density increases and therefore the interconnect

temperature increases due to joule heating. Joule heating is a result of root-square (RMS) current. As the temperature of the wire increases, the growth of the void accelerates, and eventually an open circuit occurs.

Wire width: Current density is reduced by increasing the width of the wire, and susceptibility to EM is reduced.

Impact on Physical Layout: There are particular layout strategies one can use to minimize EM effect.

The objective behind these strategies is to achieve homogenous current flow.

1. 90 degree corners should be avoided.
2. Rapid wire width reduction should be avoided.
3. depending on drive type you have to increase metal width.
4. batter use parallel path to dividing current.

What is the Litho check?

Where exactly metal shape is not printing during lithography process, in particular position, or shape, their detect hot spot errors. And correct systematic fix lithography issues during layout design…