Wednesday, March 29, 2017

Cmos Books

ANALOG VLSI DESIGN

REFERENCES:
1. Mohammed Ismail, Terri Fief, “Analog VLSI signal and Information Processing ", McGraw- Hill International Editons, 1994.

2. Malcom R.Haskard, Lan C.May, “Analog VLSI Design - NMOS and CMOS ", Prentice Hall, 1998.

3. Randall L Geiger, Phillip E. Allen, Noel K.Strader, “ VLSI Design Techniques for Analog and Digital Circuits ", Mc Graw Hill International Company, 1990.
4. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI Circuits for Telecommunication and signal Processing ", Prentice Hall, 1994

Extra Materials:

1. Mixed Analog Digital VLSI Devices and Technology by Yannis Tsividis
Download Link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTeWk2MGJSUkdnSHc/view?usp=sharing

IP BASED VLSI DESIGN

REFERENCES:
1. Wayne wolf, “Modern VLSI Design: IP-based Design”, Pearson Education,2009.
2. Qu gang, Miodrag potkonjak, “Intellectual Property Protection in VLSI Designs: Theory and Practice”, kluwer academic publishers,2003.
Download link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTQmFsV19fOHFlWXc/view?usp=sharing

SYSTEM ON CHIP DESIGN

REFERENCES
1. Wayne Wolf, “Modern VLSI Design – System – on – Chip Design”, Prentice Hall, 3rd Edition , 2008.
2. Wayne Wolf , “ Modern VLSI Design – IP based Design”, Prentice Hall, 4th Edition , 2008.
Download link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTZ21GdHZ2bHBLR28/view?usp=sharing

VLSI DESIGN TECHNIQUES

REFERENCES
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson Education ASIA, 2nd edition, 2000.
2. John P.Uyemura “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc., 2002.

3. Eugene D.Fabricius, Introduction to VLSI Design McGraw Hill International Editions, 1990.

4. Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.

5. Wayne Wolf “Modern VLSI Design System on chip. Pearson Education.2002.

LOW POWER VLSI DESIGN

REFERENCES:
1. Kaushik Roy and S.C.Prasad, “Low power CMOS VLSI circuit design”, Wiley, 2000.
2. Dimitrios Soudris, Christians Pignet, Costas Goutis, “Designing CMOS Circuits for Low Power”, Kluwer, 2002.

3. J.B.Kulo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley 1999.
4.A.P.Chandrasekaran and R.W.Broadersen, “Low power digital CMOS design”, Kluwer,1995.
5. Gary Yeap, “Practical low power digital VLSI design”, Kluwer, 1998.
6. Abdelatif Belaouar, Mohamed.I.Elmasry, “Low power digital VLSI design”, Kluwer, 1995.
7. James B.Kulo, Shih-Chia Lin, “Low voltage SOI CMOS VLSI devices and Circuits”, John Wiley and sons, inc. 2001.

8. Steven M.Rubin, “Computer Aids for VLSI Design”, Addison Wesley Publishing.
Download link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTSzA0eTh1VVFTWHc/view?usp=sharing

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

REFERENCES:
1. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th Edition, Wiley, 2009.
1.a. Solutions for Analysis and Design of Analog Integrated Circuits
2. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, Tata McGraw Hill, 2001
3. Willey M.C. Sansen, “Analog design essentials”, Springer, 2006.
4. Grebene, “Bipolar and MOS Analog Integrated circuit design”, John Wiley & sons,Inc., 2003.
5. Phillip E.Allen, DouglasR.Holberg, “CMOS Analog Circuit Design”, Second edition, Oxford University Press, 2002.
Download link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTYWk0eVlYNVV2U2c/view?usp=sharing

ASIC AND FPGA DESIGN

REFERENCES:
1. M.J.S .Smith, "Application Specific Integrated Circuits, Addison -Wesley Longman Inc., 1997
2. S. Trimberger, Field Programmable Gate Array Technology, Edr, Kluwer Academic Publications, 1994.

3. John V.Oldfield, Richard C Dore, Field Programmable Gate Arrays, Wiley Publications 1995.

4. P.K.Chan & S. Mourad, Digital Design Using Field Programmable Gate Array, Prentice Hall, 1994.

5. Parag.K.Lala, Digital System Design using Programmable Logic Devices , BSP, 2003.

6. S. Brown, R. Francis, J. Rose, Z. Vransic, Field Programmable Gate Array, Kluwer Pubin, 1992.

7. J. Old Field, R.Dorf, Field Programmable Gate Arrays, John Wiley & Sons, Newyork, 1995.

8. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Prentice Hall PTR, 2003.
9. Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004. (Chapters 1 - 4)
10. R. Rajsuman, System-on-a-Chip Design and Test. Santa Clara, CA: Artech House Publishers, 2000.

11. F. Nekoogar. Timing Verification of Application-Specific Integrated Circuits (ASICs). Prentice Hall PTR, 1999.

Extra Materials:

12. Advanced ASIC Chip Synthesis by Bhatnagar

TESTING OF VLSI CIRCUITS

REFERENCES:
1. M.Abramovici, M.A.Breuer and A.D. Friedman, “Digital systems and Testable Design”, Jaico Publishing House,2002.
2. P.K. Lala, “Digital Circuit Testing and Testability”, Academic Press, 2002.

3. M.L.Bushnell and V.D.Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2002.
4. A.L.Crouch, “Design Test for Digital IC’s and Embedded Core Systems”, Prentice Hall International, 2002.

ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY

REFERENCES:
1. V.P.Kodali, “Engineering EMC Principles, Measurements and Technologies”, IEEE Press, Newyork, 1996.
2. Clayton R.Paul,” Introduction to Electromagnetic Compatibility”, John Wiley Publications, 2008
3 . Henry W.Ott.,”Noise Reduction Techniques in Electronic Systems”, A Wiley Inter Science Publications, John Wiley and Sons, Newyork, 1988.
4. Bemhard Keiser, “Principles of Electromagnetic Compatibility”, 3rd Ed, Artech house, Norwood, 1986.

5. Don R.J.White Consultant Incorporate, “Handbook of EMI/EMC” , Vol I-V, 1988.



Extra Materials:



6. Question Bank for Electromagnetic Interference and Compatibility
Download Link - 
https://drive.google.com/file/d/0BzoKWH8M1BoTOWlCTEtNcnFfc0k/view?usp=sharing

Saturday, March 25, 2017

LOGIC LIBRARIES

Logical libraries :Format is .lib(liberty)
  1. Timing information of Standard cells,Soft macros,Hard macros.
  2. Functionality  information of Standard cells,Soft macros.
  3. And design rules like max transition ,max capacitance, max fanout.
  4. In timing information Cell delays ,Setup,Hold,Recovery,Removal time are present.
  5. Cell delay is Function of input transition and output load.
  6. Cell delay is calculated based on lookup tables.
  7. Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.
  8. Functionality  is used for Optimization Purpose.
  9. And also Contain Power information.
  10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out put voltage.
And PVT contains ------------>On Chip Variations(BC,WC)
                                ------------>Cell leakage Power
                                   ---------->Internal Power
                                   ---------->Rise Transition
                                  ----------->Fall transition
                                   ---------->>Setup rise
                                  ----------->Setup fall
                                  ----------->Hold rise
                                 ------------>Hold fall
                                 ------------>Minimum pulse width high
                                ------------->Minimum pulse width low
                                ------------->Recovery rise
                               -------------->Removal fall
                              --------------->Cell rise
                                -------------->Cell fall
                                -------------->Pin Capacitance

Cell level information 

  1. Cell name
  2. Area(represent with Nand Equ Area)
  3. Power (Funtion of input transition, Total output net Cap )
  4. Funtionality
  5. Delay
  6. Max Cap
  7. Max Trans
  8. Foot Print
And it also Contains K-Factor


And it also contain WIRE LOAD MODELS

And it contains A view(sub directory) i.e. LM(Logical Model view)view.
It contains logical libraries.


Technology file: format is .tf:
  1. It contains Name,Number conventions of layer and via
  2. It contains Physical,electrical characteristics of  layer and via
  3. In Physical characteristics Min width,Min Spacing,Min Hight are present.
  4. In Electrical characteristics Max Current Density is present.
  5. Units and Precisions of layer and via .
  6. Colors and pattern of layer and via .
  7. Physical Design rules of layer and via
  8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

Layer Info :
  1. Mask Name
  2. Visible
  3. Selectable
  4. Line Style(Solid)
  5. Patteren 
  6. Pitch
  7. Cut Layer 

Physical libraries: format is .lef(Layout Exchange Format):
  1. physical information of std cells,macros,pads.
  2. Pin information.
  3. Define unit tile(sites) placement.
  4. Minimum Width of Resolution.
  5. Hight of the placement Rows .
  6. Preferred routing Directions.
  7. Pitch of the routing tracks.
  8. Antena Rules.
  9. Routing Blockages,Macro Blockage
Macro/Stad Cells :-------------->Cell neame
                                -------------->Size(Dimensions,Area)
                                 ------------->Pin
                                 ------------->Port
                                  ------------->Layer
                                  ------------->Direction
                                  
Pins information :  --------------->Direction(Input,Output,INOUT)
                                 --------------->Use(Signal,Power,Ground)
                                 --------------->Antena Gate Area
                                 --------------->layer
  


LEFs are 3 Types :  .Macro lef (Macro Info)
                                  .StdCell lef(Standard Cell Info )
                                  .Tech lef(Layer,Via Info)


In physical info height,area,width are present.
and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route


FINAL VERIFICATION:
  1. PARASITICS EXTRACTION:IT EXTRACT R,C VALUES FOR GETTING ORIGINAL DELAYS. TOOL:STAR RC XT LICENCE
  2. TIMING VERIFICATION:IT IS FIND BY USING PRIME TIME TOOL. 
  3. LVS ,ERC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.
  4. DRC CHECKS:THESE IS FIND OUT BY USING CALIBRE,HERCULIES TOOLS.

AFTER VERIFICATION:
  1. AFTER THIS WE RELEASE THE GDS FILE 
  2. IN THIS WE HAVE ALL POLYGONS INFORMATION IS PRESENT.

AFTER GDS 

AFTER THIS WE ARE FINALLY BASE TAPE OUT(BTO).

AFTER BASE TAPE OUT WE WILL DO METAL TAPE OUT(MTO).


Verification checks

DRC : Design rule check. Design rule are strict guideline for drawing layout Minimum width Minimum spacing Minimum extension Min...