ASIC DESIGN FLOW
IntroductionIntegrated Circuits are made from Silicon wafer, with each holding of hundreds of die. The first silicon chip or integrated circuit consisting of many transistors fabricated on the same piece of silicon, was made at Fairchild in 1959.More recent developments have been towards miniaturization-packing more and more active components or gates on to a single chip of silicon. The level of device complexity is usually referred to as a scale of integration. The evolution from scale integration (SSI), through large-scale integration (LSI), to very large scale integration (VLSI) has already occurred, and the scale is running out of adjectives. The scale of integration is based on the number of logic elements that constitute a device. An ASIC is an Application Specific Integrated Circuit. An Integrated Circuit designed is called an ASIC if We design the ASIC for the specific application.
Examples of ASIC chip design for a satellite, chip design for car.
The following paragraphs will describe the types of ASIC''s
1. Full Custom ASIC
2. Standard Cell ASIC
3. Gate Array ASIC
Full Custom ASIC
For this type of ASIC, All mask layers are customized in a full custom ASIC. It only makes sense to design a full custom IC if there are no libraries available, the full custom design highest performance and lowest part cost ( small die size ) with the
disadvantages of increased design time, complexity, the designer designs all or some of the logic cells, layout for that one chip. The designer does not used predefined gates in the design.
Standard Cell ASIC
The designer uses predesigned logic cells such as AND gate, NOR gate, etc.
These gates are called Standard Cells. The advantage of Standard Cell ASIC’s is that the designers save time, money and reduce the risk by using a predesigned and pre-tested Standard Cell Library. Also each Standard Cell can be optimized individually. The Standard Cell Libraries is designed using the Full Custom Methodology, but you can use these already designed libraries in the design. This design style gives a designer the same flexibility as the Full Custom design, but reduces the risk.
Standard Cell ASIC Gate Array ASIC
In this type of ASIC, the transistors are predefined in the silicon wafer. The predefined pattern of transistors on the gate array is called a base array and the smallest element in the base array is called a base cell. The base cell layout is same for each logic cell, only the interconnect between the cells and inside the cells is customized.Thefollowing are the types of gate arrays:
a. Channeled Gate Array
b. Channelless Gate Array
C. Structured Gate Array
ASIC stands for Application Specific Integrated Circuit. A chip that is custom
designed for a specific application rather than a general-purpose chip such as a
microprocessor.
ASIC design flow is associated with the following:
a. Layout/Design
b. Characterization
c. CAD Modelling
Standard cell libraries are associated with various functionalities like not, nor, nand, and, or etc. However, the libraries associated with the so called “PPA” goals:
P => Performance
P => Power
A => Area
Size.
Integrated circuits are much smaller both transistors and wires are shrunk to
micrometer sizes, compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages in speed and power consumption, since
smaller components have smaller parasitic resistances, capacitances, and inductances.
Speed.
Signals can be switched between logic 0 and logic 1 much quicker within a chip
than they can between chips. Communication within a chip can occur hundreds of times faster than communication between chips on a printed circuit board. The high speed of circuits on-chip is due to their small size—smaller components and wires have smaller parasitic capacitances to slow down the signal.
Power consumption.
Logic operations within a chip also take much less power. Once again, lower power consumption is largely due to the small size of circuits on the chip smaller parasitic capacitances and resistances require less power to drive them.
Lower power consumption.
Replacing a handful of standard parts with a single chip reduces total power consumption. Reducing power consumption has a ripple effect on the rest of the system: a smaller, cheaper power supply can be used; since less power consumption means less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for electromagnetic shielding may be feasible.
Reduced cost.
Reducing the number of components, the power supply requirements, cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a system built from custom ICs can be less, even though the individual ICs cost more than the standard parts they replace. Understanding why integrated circuit technology has such profound influence on the design of digital
systems requires understanding both the technology of IC manufacturing and the
economics of ICs and digital systems. Any developed cell should meet the above required parameters to be successfully implemented in a chip.
Before we actually put the layout, we first design the circuit to come up with the
schematic diagram. This is basically associated with designing the width of the transistor to meet the various specifications in the form of delay, input capacitance, rise time, fall time, slew etc keeping in mind the fixed value of load. Once we are ready with the schematic, the next important task is to put the layout for the designed schematic. In digital field, we put the layout with reference to the available tracks such as single height, double height etc. However, the height of the track is fixed, i.e., Y direction remains constant while we extend the layout in the X direction, horizontally. Once the layouting is done, it is checked against Design Rule Checks (DRC) to see if there are any errors.
Foot core/Tap cells
form an integral part of the layout aspect. It is basically associated with the bulk connections of the device. It is mandatory to include foot core in the layout without which the DRC remains unclean. It is always present in the -ve quadrant while the layout is expected to be present in the +ve quadrant as a general convention. This is followed by the conversion of the layout into Geometrical Data Stream(gds) format file. The gds file is basically a binary stream of the data that contains the encrypted version of the layout. This is to make the data compatible with the subsequent stage of ASIC flow namely characterisation. It is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork.
It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photo masks. There is another file format which contains basically the same kind of information as that of gds file. This file is called laff file. It stands for LISP Archival File Format. This is the readable format of the gds file. This contains the parametric values like Cin, resistance, source area, drain area etc in the form of the rectangle. gds/laff files are fed to one of the extraction tool which give us the netlist. Netlist is used for characterisation whose o/p is .lib file. The obtained netlist is however, used in LVS check of the lay out.
Another important aspect of the laff file is that it helps us to obtain lef file.
A LEF file contains the following information:
1. Pin information
2. Metal Connections
3. Vdd,Vss information
4 Routability and connectivity.
This file basically is used by the top level people to build and enhance the model.
Characterization:-
It is associated with calculating the various parameters like Cin, delay, power, set up and hold time values against the specified values to check for the precision in the lay out.
CAD modeling :-
It is done to check the functionality of the cell. It makes use of
VERILOG coding language to test the functionality. The output file is saved in .v file
format. This process is done parallely to lay outing.
Various different kinds of checks are made during the checks :
LVS check :-
Layout Versus Schematic check: Here, we see if all the specifications mentioned in the schematic of the circuit like width, length etc matches with the layout or not.
DRC check:-
This is the check to meet the various criteria of the tool we are using.
EM/Electromigration check:-
This is to check the flow of the current flowing in the metal to predict the life of the chip.
COMPAT check:-
This is basically the boundary DRC.
SPIVER check:-
This gives the functionality between verilog and schematic. This makes use of the built in truth table to test the obtained output against the expected output.
SV_SPICE :-
It checks the functionality of the cell. It checks only the transistor connections without giving the RC values information.
